/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_CM_MIPI_CSI_3PHASE_H
#define TITAN170_CM_MIPI_CSI_3PHASE_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define CM_MIPI_CSI_3PHASE_REGS_FIRST 0x0 

#define CM_MIPI_CSI_3PHASE_REGS_LAST 0xcec 

#define CM_MIPI_CSI_3PHASE_REGS_COUNT 0x2e4 

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0 0x0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1 0x4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2 0x8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3 0xc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4 0x10  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5 0x14  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6 0x18  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7 0x1c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8 0x20  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9 0x24  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10 0x28  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11 0x2c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12 0x30  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13 0x34  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14 0x38  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15 0x3c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16 0x40  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17 0x44  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18 0x48  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19 0x4c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20 0x50  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21 0x54  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22 0x58  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23 0x5c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24 0x60  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25 0x64  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26 0x68  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27 0x6c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28 0x70  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29 0x74  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30 0x78  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31 0x7c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32 0x80  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33 0x84  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34 0x88  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35 0x8c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0 0x90  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1 0x94  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2 0x98  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3 0x9c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4 0xa0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5 0xa4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6 0xa8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7 0xac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8 0xb0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9 0xb4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10 0xb8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11 0xbc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12 0xc0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13 0xc4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14 0xc8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15 0xcc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0 0x100  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1 0x104  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2 0x108  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3 0x10c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4 0x110  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5 0x114  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6 0x118  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7 0x11c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8 0x120  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9 0x124  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10 0x128  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11 0x12c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12 0x130  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13 0x134  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14 0x138  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15 0x13c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16 0x140  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17 0x144  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18 0x148  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19 0x14c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20 0x150  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21 0x154  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22 0x158  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23 0x15c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24 0x160  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25 0x164  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26 0x168  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27 0x16c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28 0x170  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29 0x174  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30 0x178  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31 0x17c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32 0x180  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33 0x184  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34 0x188  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35 0x18c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36 0x190  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37 0x194  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38 0x198  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39 0x19c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40 0x1a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41 0x1a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42 0x1a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43 0x1ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44 0x1b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45 0x1b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46 0x1b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47 0x1bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48 0x1c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49 0x1c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50 0x1c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51 0x1cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52 0x1d0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53 0x1d4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54 0x1d8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55 0x1dc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0 0x1e0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1 0x1e4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2 0x1e8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3 0x1ec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4 0x1f0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5 0x1f4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6 0x1f8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7 0x1fc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0 0x200  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1 0x204  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2 0x208  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3 0x20c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4 0x210  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5 0x214  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6 0x218  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7 0x21c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8 0x220  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9 0x224  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10 0x228  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11 0x22c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12 0x230  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13 0x234  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14 0x238  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15 0x23c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16 0x240  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17 0x244  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18 0x248  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19 0x24c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20 0x250  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21 0x254  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22 0x258  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23 0x25c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24 0x260  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25 0x264  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26 0x268  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27 0x26c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28 0x270  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29 0x274  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30 0x278  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31 0x27c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32 0x280  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33 0x284  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34 0x288  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35 0x28c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0 0x290  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1 0x294  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2 0x298  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3 0x29c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4 0x2a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5 0x2a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6 0x2a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7 0x2ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8 0x2b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9 0x2b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10 0x2b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11 0x2bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12 0x2c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13 0x2c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14 0x2c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15 0x2cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0 0x300  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1 0x304  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2 0x308  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3 0x30c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4 0x310  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5 0x314  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6 0x318  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7 0x31c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8 0x320  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9 0x324  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10 0x328  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11 0x32c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12 0x330  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13 0x334  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14 0x338  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15 0x33c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16 0x340  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17 0x344  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18 0x348  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19 0x34c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20 0x350  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21 0x354  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22 0x358  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23 0x35c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24 0x360  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25 0x364  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26 0x368  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27 0x36c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28 0x370  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29 0x374  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30 0x378  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31 0x37c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32 0x380  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33 0x384  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34 0x388  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35 0x38c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36 0x390  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37 0x394  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38 0x398  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39 0x39c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40 0x3a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41 0x3a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42 0x3a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43 0x3ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44 0x3b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45 0x3b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46 0x3b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47 0x3bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48 0x3c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49 0x3c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50 0x3c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51 0x3cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52 0x3d0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53 0x3d4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54 0x3d8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55 0x3dc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0 0x3e0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1 0x3e4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2 0x3e8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3 0x3ec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4 0x3f0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5 0x3f4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6 0x3f8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7 0x3fc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0 0x400  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1 0x404  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2 0x408  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3 0x40c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4 0x410  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5 0x414  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6 0x418  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7 0x41c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8 0x420  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9 0x424  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10 0x428  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11 0x42c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12 0x430  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13 0x434  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14 0x438  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15 0x43c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16 0x440  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17 0x444  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18 0x448  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19 0x44c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20 0x450  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21 0x454  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22 0x458  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23 0x45c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24 0x460  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25 0x464  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26 0x468  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27 0x46c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28 0x470  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29 0x474  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30 0x478  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31 0x47c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32 0x480  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33 0x484  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34 0x488  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35 0x48c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0 0x490  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1 0x494  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2 0x498  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3 0x49c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4 0x4a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5 0x4a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6 0x4a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7 0x4ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8 0x4b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9 0x4b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10 0x4b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11 0x4bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12 0x4c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13 0x4c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14 0x4c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15 0x4cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0 0x500  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0_CSI_3PHASE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1 0x504  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1_CSI_3PHASE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2 0x508  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2_CSI_3PHASE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3 0x50c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3_CSI_3PHASE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4 0x510  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4_CSI_3PHASE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5 0x514  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5_CSI_3PHASE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6 0x518  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6_CSI_3PHASE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7 0x51c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7_CSI_3PHASE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8 0x520  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8_CSI_3PHASE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9 0x524  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9_CSI_3PHASE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10 0x528  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10_CSI_3PHASE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11 0x52c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11_CSI_3PHASE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12 0x530  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12_CSI_3PHASE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13 0x534  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13_CSI_3PHASE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14 0x538  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14_CSI_3PHASE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15 0x53c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15_CSI_3PHASE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16 0x540  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16_CSI_3PHASE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17 0x544  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17_CSI_3PHASE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18 0x548  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18_CSI_3PHASE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19 0x54c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19_CSI_3PHASE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20 0x550  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20_CSI_3PHASE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21 0x554  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21_CSI_3PHASE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22 0x558  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22_CSI_3PHASE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23 0x55c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23_CSI_3PHASE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24 0x560  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24_CSI_3PHASE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25 0x564  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25_CSI_3PHASE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26 0x568  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26_CSI_3PHASE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27 0x56c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27_CSI_3PHASE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28 0x570  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28_CSI_3PHASE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29 0x574  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29_CSI_3PHASE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30 0x578  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30_CSI_3PHASE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31 0x57c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31_CSI_3PHASE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32 0x580  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32_CSI_3PHASE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33 0x584  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33_CSI_3PHASE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34 0x588  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34_CSI_3PHASE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35 0x58c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35_CSI_3PHASE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36 0x590  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36_CSI_3PHASE_CTRL36_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37 0x594  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37_CSI_3PHASE_CTRL37_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38 0x598  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38_CSI_3PHASE_CTRL38_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39 0x59c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39_CSI_3PHASE_CTRL39_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40 0x5a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40_CSI_3PHASE_CTRL40_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41 0x5a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41_CSI_3PHASE_CTRL41_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42 0x5a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42_CSI_3PHASE_CTRL42_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43 0x5ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43_CSI_3PHASE_CTRL43_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44 0x5b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44_CSI_3PHASE_CTRL44_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45 0x5b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45_CSI_3PHASE_CTRL45_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46 0x5b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46_CSI_3PHASE_CTRL46_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47 0x5bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47_CSI_3PHASE_CTRL47_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48 0x5c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48_CSI_3PHASE_CTRL48_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49 0x5c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49_CSI_3PHASE_CTRL49_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50 0x5c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50_CSI_3PHASE_CTRL50_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51 0x5cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51_CSI_3PHASE_CTRL51_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52 0x5d0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52_CSI_3PHASE_CTRL52_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53 0x5d4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53_CSI_3PHASE_CTRL53_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54 0x5d8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54_CSI_3PHASE_CTRL54_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55 0x5dc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55_CSI_3PHASE_CTRL55_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0 0x5e0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0_CSI_3PHASE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1 0x5e4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1_CSI_3PHASE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2 0x5e8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2_CSI_3PHASE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3 0x5ec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3_CSI_3PHASE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4 0x5f0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4_CSI_3PHASE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5 0x5f4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5_CSI_3PHASE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6 0x5f8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6_CSI_3PHASE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7 0x5fc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7_CSI_3PHASE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0 0x600  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1 0x604  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2 0x608  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3 0x60c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4 0x610  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5 0x614  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6 0x618  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7 0x61c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8 0x620  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9 0x624  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10 0x628  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11 0x62c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12 0x630  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13 0x634  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14 0x638  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15 0x63c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16 0x640  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17 0x644  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18 0x648  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19 0x64c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20 0x650  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21 0x654  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22 0x658  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23 0x65c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24 0x660  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25 0x664  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26 0x668  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27 0x66c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28 0x670  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29 0x674  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30 0x678  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31 0x67c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32 0x680  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33 0x684  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34 0x688  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35 0x68c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0 0x690  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1 0x694  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2 0x698  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3 0x69c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4 0x6a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5 0x6a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6 0x6a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7 0x6ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8 0x6b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9 0x6b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10 0x6b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11 0x6bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12 0x6c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13 0x6c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14 0x6c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15 0x6cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0 0x700  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0_CSI_LANE_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1 0x704  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1_CSI_LANE_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2 0x708  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2_CSI_LANE_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3 0x70c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3_CSI_LANE_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4 0x710  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4_CSI_LANE_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5 0x714  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5_CSI_LANE_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6 0x718  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6_CSI_LANE_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7 0x71c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7_CSI_LANE_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8 0x720  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8_CSI_LANE_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9 0x724  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9_CSI_LANE_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10 0x728  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10_CSI_LANE_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11 0x72c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11_CSI_LANE_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12 0x730  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12_CSI_LANE_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13 0x734  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13_CSI_LANE_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14 0x738  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14_CSI_LANE_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15 0x73c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15_CSI_LANE_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16 0x740  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16_CSI_LANE_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17 0x744  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17_CSI_LANE_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18 0x748  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18_CSI_LANE_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19 0x74c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19_CSI_LANE_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20 0x750  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20_CSI_LANE_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21 0x754  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21_CSI_LANE_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22 0x758  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22_CSI_LANE_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23 0x75c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23_CSI_LANE_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24 0x760  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24_CSI_LANE_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25 0x764  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25_CSI_LANE_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26 0x768  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26_CSI_LANE_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27 0x76c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27_CSI_LANE_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28 0x770  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28_CSI_LANE_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29 0x774  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29_CSI_LANE_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30 0x778  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30_CSI_LANE_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31 0x77c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31_CSI_LANE_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32 0x780  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32_CSI_LANE_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33 0x784  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33_CSI_LANE_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34 0x788  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34_CSI_LANE_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35 0x78c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35_CSI_LANE_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0 0x790  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0_CSI_LANE_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1 0x794  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1_CSI_LANE_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2 0x798  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2_CSI_LANE_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3 0x79c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3_CSI_LANE_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4 0x7a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4_CSI_LANE_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5 0x7a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5_CSI_LANE_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6 0x7a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6_CSI_LANE_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7 0x7ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7_CSI_LANE_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8 0x7b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8_CSI_LANE_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9 0x7b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9_CSI_LANE_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10 0x7b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10_CSI_LANE_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11 0x7bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11_CSI_LANE_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12 0x7c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12_CSI_LANE_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13 0x7c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13_CSI_LANE_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14 0x7c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14_CSI_LANE_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15 0x7cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15_CSI_LANE_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0 0x800  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0_CSI_COMMON_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0_CSI_COMMON_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1 0x804  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1_CSI_COMMON_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1_CSI_COMMON_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2 0x808  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2_CSI_COMMON_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2_CSI_COMMON_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3 0x80c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3_CSI_COMMON_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3_CSI_COMMON_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4 0x810  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4_CSI_COMMON_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4_CSI_COMMON_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5 0x814  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_CSI_COMMON_CTRL5_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6 0x818  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_CSI_COMMON_CTRL6_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7 0x81c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_CSI_COMMON_CTRL7_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8 0x820  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8_CSI_COMMON_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8_CSI_COMMON_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9 0x824  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9_CSI_COMMON_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9_CSI_COMMON_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10 0x828  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_CSI_COMMON_CTRL10_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11 0x82c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11_CSI_COMMON_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11_CSI_COMMON_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12 0x830  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12_CSI_COMMON_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12_CSI_COMMON_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13 0x834  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13_CSI_COMMON_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13_CSI_COMMON_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14 0x838  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14_CSI_COMMON_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14_CSI_COMMON_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15 0x83c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15_CSI_COMMON_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15_CSI_COMMON_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16 0x840  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16_CSI_COMMON_CTRL16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16_CSI_COMMON_CTRL16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17 0x844  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17_CSI_COMMON_CTRL17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17_CSI_COMMON_CTRL17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18 0x848  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18_CSI_COMMON_CTRL18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18_CSI_COMMON_CTRL18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19 0x84c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19_CSI_COMMON_CTRL19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19_CSI_COMMON_CTRL19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20 0x850  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20_CSI_COMMON_CTRL20_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20_CSI_COMMON_CTRL20_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21 0x854  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21_CSI_COMMON_CTRL21_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21_CSI_COMMON_CTRL21_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22 0x858  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22_CSI_COMMON_CTRL22_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22_CSI_COMMON_CTRL22_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23 0x85c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23_CSI_COMMON_CTRL23_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23_CSI_COMMON_CTRL23_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24 0x860  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24_CSI_COMMON_CTRL24_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24_CSI_COMMON_CTRL24_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25 0x864  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25_CSI_COMMON_CTRL25_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25_CSI_COMMON_CTRL25_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26 0x868  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26_CSI_COMMON_CTRL26_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26_CSI_COMMON_CTRL26_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27 0x86c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27_CSI_COMMON_CTRL27_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27_CSI_COMMON_CTRL27_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28 0x870  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28_CSI_COMMON_CTRL28_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28_CSI_COMMON_CTRL28_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29 0x874  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29_CSI_COMMON_CTRL29_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29_CSI_COMMON_CTRL29_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30 0x878  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30_CSI_COMMON_CTRL30_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30_CSI_COMMON_CTRL30_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31 0x87c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31_CSI_COMMON_CTRL31_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31_CSI_COMMON_CTRL31_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32 0x880  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32_CSI_COMMON_CTRL32_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32_CSI_COMMON_CTRL32_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33 0x884  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33_CSI_COMMON_CTRL33_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33_CSI_COMMON_CTRL33_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34 0x888  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34_CSI_COMMON_CTRL34_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34_CSI_COMMON_CTRL34_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35 0x88c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35_CSI_COMMON_CTRL35_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35_CSI_COMMON_CTRL35_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36 0x890  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36_CSI_COMMON_CTRL36_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36_CSI_COMMON_CTRL36_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37 0x894  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37_CSI_COMMON_CTRL37_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37_CSI_COMMON_CTRL37_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38 0x898  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38_CSI_COMMON_CTRL38_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38_CSI_COMMON_CTRL38_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39 0x89c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39_CSI_COMMON_CTRL39_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39_CSI_COMMON_CTRL39_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40 0x8a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40_CSI_COMMON_CTRL40_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40_CSI_COMMON_CTRL40_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41 0x8a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41_CSI_COMMON_CTRL41_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41_CSI_COMMON_CTRL41_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42 0x8a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42_CSI_COMMON_CTRL42_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42_CSI_COMMON_CTRL42_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43 0x8ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43_CSI_COMMON_CTRL43_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43_CSI_COMMON_CTRL43_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0 0x8b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_CSI_COMMON_STATUS0_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1 0x8b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_CSI_COMMON_STATUS1_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2 0x8b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_CSI_COMMON_STATUS2_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3 0x8bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_CSI_COMMON_STATUS3_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4 0x8c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_CSI_COMMON_STATUS4_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5 0x8c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_CSI_COMMON_STATUS5_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6 0x8c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_CSI_COMMON_STATUS6_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7 0x8cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_CSI_COMMON_STATUS7_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8 0x8d0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_CSI_COMMON_STATUS8_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9 0x8d4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_CSI_COMMON_STATUS9_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10 0x8d8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_0_MASK 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_1_MASK 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_1_SHIFT 0x1
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_2_MASK 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_2_SHIFT 0x2
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_3_MASK 0x8
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_3_SHIFT 0x3
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_4_MASK 0x10
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_4_SHIFT 0x4
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_5_MASK 0x20
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_5_SHIFT 0x5
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_6_MASK 0x40
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_6_SHIFT 0x6
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_7_MASK 0x80
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_CSI_COMMON_STATUS10_7_SHIFT 0x7
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11 0x8dc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11_CSI_COMMON_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11_CSI_COMMON_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12 0x8e0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12_CSI_COMMON_STATUS12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12_CSI_COMMON_STATUS12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13 0x8e4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13_CSI_COMMON_STATUS13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13_CSI_COMMON_STATUS13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14 0x8e8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14_CSI_COMMON_STATUS14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14_CSI_COMMON_STATUS14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15 0x8ec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15_CSI_COMMON_STATUS15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15_CSI_COMMON_STATUS15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16 0x8f0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16_CSI_COMMON_STATUS16_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16_CSI_COMMON_STATUS16_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17 0x8f4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17_CSI_COMMON_STATUS17_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17_CSI_COMMON_STATUS17_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18 0x8f8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18_CSI_COMMON_STATUS18_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18_CSI_COMMON_STATUS18_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19 0x8fc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19_CSI_COMMON_STATUS19_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19_CSI_COMMON_STATUS19_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0 0x900  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1 0x904  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2 0x908  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3 0x90c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4 0x910  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5 0x914  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6 0x918  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7 0x91c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8 0x920  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9 0x924  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10 0x928  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11 0x92c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12 0x930  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13 0x934  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14 0x938  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15 0x93c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0 0x940  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1 0x944  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2 0x948  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3 0x94c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4 0x950  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5 0x954  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6 0x958  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7 0x95c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8 0x960  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9 0x964  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10 0x968  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11 0x96c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0 0x980  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1 0x984  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2 0x988  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3 0x98c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4 0x990  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5 0x994  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6 0x998  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7 0x99c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8 0x9a0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9 0x9a4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10 0x9a8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11 0x9ac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12 0x9b0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13 0x9b4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14 0x9b8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15 0x9bc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0 0x9c0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1 0x9c4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2 0x9c8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3 0x9cc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4 0x9d0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5 0x9d4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6 0x9d8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7 0x9dc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8 0x9e0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9 0x9e4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10 0x9e8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11 0x9ec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0 0xa00  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1 0xa04  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2 0xa08  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3 0xa0c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4 0xa10  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5 0xa14  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6 0xa18  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7 0xa1c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8 0xa20  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9 0xa24  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10 0xa28  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11 0xa2c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12 0xa30  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13 0xa34  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14 0xa38  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15 0xa3c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0 0xa40  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1 0xa44  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2 0xa48  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3 0xa4c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4 0xa50  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5 0xa54  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6 0xa58  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7 0xa5c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8 0xa60  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9 0xa64  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10 0xa68  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11 0xa6c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0 0xa80  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1 0xa84  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2 0xa88  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3 0xa8c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4 0xa90  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5 0xa94  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6 0xa98  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7 0xa9c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8 0xaa0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9 0xaa4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10 0xaa8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11 0xaac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12 0xab0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13 0xab4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14 0xab8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15 0xabc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0 0xac0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1 0xac4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2 0xac8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3 0xacc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4 0xad0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5 0xad4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6 0xad8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7 0xadc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8 0xae0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9 0xae4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10 0xae8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11 0xaec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0 0xb00  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1 0xb04  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2 0xb08  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3 0xb0c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4 0xb10  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5 0xb14  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6 0xb18  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7 0xb1c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8 0xb20  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9 0xb24  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10 0xb28  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11 0xb2c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12 0xb30  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13 0xb34  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14 0xb38  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15 0xb3c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0 0xb40  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1 0xb44  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2 0xb48  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3 0xb4c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4 0xb50  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5 0xb54  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6 0xb58  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7 0xb5c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8 0xb60  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9 0xb64  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10 0xb68  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11 0xb6c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0 0xb80  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1 0xb84  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2 0xb88  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3 0xb8c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4 0xb90  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5 0xb94  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6 0xb98  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7 0xb9c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8 0xba0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9 0xba4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10 0xba8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11 0xbac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12 0xbb0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13 0xbb4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14 0xbb8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15 0xbbc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0 0xbc0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1 0xbc4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2 0xbc8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3 0xbcc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4 0xbd0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5 0xbd4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6 0xbd8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7 0xbdc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8 0xbe0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9 0xbe4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10 0xbe8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11 0xbec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0 0xc00  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1 0xc04  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2 0xc08  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3 0xc0c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4 0xc10  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5 0xc14  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6 0xc18  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7 0xc1c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8 0xc20  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9 0xc24  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10 0xc28  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11 0xc2c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12 0xc30  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13 0xc34  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14 0xc38  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15 0xc3c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0 0xc40  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1 0xc44  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2 0xc48  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3 0xc4c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4 0xc50  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5 0xc54  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6 0xc58  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7 0xc5c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8 0xc60  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9 0xc64  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10 0xc68  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11 0xc6c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0 0xc80  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0_CSI_EXTRA_CTRL0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1 0xc84  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1_CSI_EXTRA_CTRL1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2 0xc88  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2_CSI_EXTRA_CTRL2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3 0xc8c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3_CSI_EXTRA_CTRL3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4 0xc90  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4_CSI_EXTRA_CTRL4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5 0xc94  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5_CSI_EXTRA_CTRL5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6 0xc98  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6_CSI_EXTRA_CTRL6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7 0xc9c  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7_CSI_EXTRA_CTRL7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8 0xca0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8_CSI_EXTRA_CTRL8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9 0xca4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9_CSI_EXTRA_CTRL9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10 0xca8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10_CSI_EXTRA_CTRL10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11 0xcac  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11_CSI_EXTRA_CTRL11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12 0xcb0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12_CSI_EXTRA_CTRL12_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13 0xcb4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13_CSI_EXTRA_CTRL13_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14 0xcb8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14_CSI_EXTRA_CTRL14_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15 0xcbc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15_CSI_EXTRA_CTRL15_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0 0xcc0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0_CSI_EXTRA_STATUS0_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1 0xcc4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1_CSI_EXTRA_STATUS1_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2 0xcc8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2_CSI_EXTRA_STATUS2_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3 0xccc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3_CSI_EXTRA_STATUS3_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4 0xcd0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4_CSI_EXTRA_STATUS4_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5 0xcd4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5_CSI_EXTRA_STATUS5_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6 0xcd8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6_CSI_EXTRA_STATUS6_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7 0xcdc  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7_CSI_EXTRA_STATUS7_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8 0xce0  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8_CSI_EXTRA_STATUS8_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9 0xce4  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9_CSI_EXTRA_STATUS9_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10 0xce8  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10_CSI_EXTRA_STATUS10_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10_UNUSED0_SHIFT 0x8

#define regCM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11 0xcec  /*register offset*/
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_MASK 0xff
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11_CSI_EXTRA_STATUS11_SHIFT 0x0
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11_UNUSED0_MASK 0xffffff00
#define CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11_UNUSED0_SHIFT 0x8

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  CSI_LANE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL0;

typedef struct{
    unsigned  CSI_LANE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL1;

typedef struct{
    unsigned  CSI_LANE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL2;

typedef struct{
    unsigned  CSI_LANE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL3;

typedef struct{
    unsigned  CSI_LANE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL4;

typedef struct{
    unsigned  CSI_LANE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL5;

typedef struct{
    unsigned  CSI_LANE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL6;

typedef struct{
    unsigned  CSI_LANE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL7;

typedef struct{
    unsigned  CSI_LANE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL8;

typedef struct{
    unsigned  CSI_LANE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL9;

typedef struct{
    unsigned  CSI_LANE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL10;

typedef struct{
    unsigned  CSI_LANE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL11;

typedef struct{
    unsigned  CSI_LANE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL12;

typedef struct{
    unsigned  CSI_LANE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL13;

typedef struct{
    unsigned  CSI_LANE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL14;

typedef struct{
    unsigned  CSI_LANE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL15;

typedef struct{
    unsigned  CSI_LANE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL16;

typedef struct{
    unsigned  CSI_LANE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL17;

typedef struct{
    unsigned  CSI_LANE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL18;

typedef struct{
    unsigned  CSI_LANE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL19;

typedef struct{
    unsigned  CSI_LANE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL20;

typedef struct{
    unsigned  CSI_LANE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL21;

typedef struct{
    unsigned  CSI_LANE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL22;

typedef struct{
    unsigned  CSI_LANE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL23;

typedef struct{
    unsigned  CSI_LANE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL24;

typedef struct{
    unsigned  CSI_LANE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL25;

typedef struct{
    unsigned  CSI_LANE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL26;

typedef struct{
    unsigned  CSI_LANE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL27;

typedef struct{
    unsigned  CSI_LANE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL28;

typedef struct{
    unsigned  CSI_LANE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL29;

typedef struct{
    unsigned  CSI_LANE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL30;

typedef struct{
    unsigned  CSI_LANE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL31;

typedef struct{
    unsigned  CSI_LANE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL32;

typedef struct{
    unsigned  CSI_LANE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL33;

typedef struct{
    unsigned  CSI_LANE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL34;

typedef struct{
    unsigned  CSI_LANE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_CTRL35;

typedef struct{
    unsigned  CSI_LANE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS0;

typedef struct{
    unsigned  CSI_LANE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS1;

typedef struct{
    unsigned  CSI_LANE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS2;

typedef struct{
    unsigned  CSI_LANE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS3;

typedef struct{
    unsigned  CSI_LANE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS4;

typedef struct{
    unsigned  CSI_LANE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS5;

typedef struct{
    unsigned  CSI_LANE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS6;

typedef struct{
    unsigned  CSI_LANE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS8;

typedef struct{
    unsigned  CSI_LANE_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS9;

typedef struct{
    unsigned  CSI_LANE_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS10;

typedef struct{
    unsigned  CSI_LANE_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS11;

typedef struct{
    unsigned  CSI_LANE_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS12;

typedef struct{
    unsigned  CSI_LANE_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS13;

typedef struct{
    unsigned  CSI_LANE_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS14;

typedef struct{
    unsigned  CSI_LANE_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln0_csi_2phase_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN0_CSI_2PHASE_STATUS15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL0;

typedef struct{
    unsigned  CSI_3PHASE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL1;

typedef struct{
    unsigned  CSI_3PHASE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL2;

typedef struct{
    unsigned  CSI_3PHASE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL3;

typedef struct{
    unsigned  CSI_3PHASE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL4;

typedef struct{
    unsigned  CSI_3PHASE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL5;

typedef struct{
    unsigned  CSI_3PHASE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL6;

typedef struct{
    unsigned  CSI_3PHASE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL7;

typedef struct{
    unsigned  CSI_3PHASE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL8;

typedef struct{
    unsigned  CSI_3PHASE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL9;

typedef struct{
    unsigned  CSI_3PHASE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL10;

typedef struct{
    unsigned  CSI_3PHASE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL11;

typedef struct{
    unsigned  CSI_3PHASE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL12;

typedef struct{
    unsigned  CSI_3PHASE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL13;

typedef struct{
    unsigned  CSI_3PHASE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL14;

typedef struct{
    unsigned  CSI_3PHASE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL16;

typedef struct{
    unsigned  CSI_3PHASE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL17;

typedef struct{
    unsigned  CSI_3PHASE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL18;

typedef struct{
    unsigned  CSI_3PHASE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL19;

typedef struct{
    unsigned  CSI_3PHASE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL20;

typedef struct{
    unsigned  CSI_3PHASE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL21;

typedef struct{
    unsigned  CSI_3PHASE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL22;

typedef struct{
    unsigned  CSI_3PHASE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL23;

typedef struct{
    unsigned  CSI_3PHASE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL24;

typedef struct{
    unsigned  CSI_3PHASE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL25;

typedef struct{
    unsigned  CSI_3PHASE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL26;

typedef struct{
    unsigned  CSI_3PHASE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL27;

typedef struct{
    unsigned  CSI_3PHASE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL28;

typedef struct{
    unsigned  CSI_3PHASE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL29;

typedef struct{
    unsigned  CSI_3PHASE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL30;

typedef struct{
    unsigned  CSI_3PHASE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL31;

typedef struct{
    unsigned  CSI_3PHASE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL32;

typedef struct{
    unsigned  CSI_3PHASE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL33;

typedef struct{
    unsigned  CSI_3PHASE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL34;

typedef struct{
    unsigned  CSI_3PHASE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL35;

typedef struct{
    unsigned  CSI_3PHASE_CTRL36 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl36;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl36 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL36;

typedef struct{
    unsigned  CSI_3PHASE_CTRL37 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl37;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl37 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL37;

typedef struct{
    unsigned  CSI_3PHASE_CTRL38 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl38;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl38 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL38;

typedef struct{
    unsigned  CSI_3PHASE_CTRL39 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl39;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl39 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL39;

typedef struct{
    unsigned  CSI_3PHASE_CTRL40 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl40;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl40 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL40;

typedef struct{
    unsigned  CSI_3PHASE_CTRL41 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl41;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl41 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL41;

typedef struct{
    unsigned  CSI_3PHASE_CTRL42 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl42;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl42 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL42;

typedef struct{
    unsigned  CSI_3PHASE_CTRL43 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl43;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl43 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL43;

typedef struct{
    unsigned  CSI_3PHASE_CTRL44 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl44;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl44 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL44;

typedef struct{
    unsigned  CSI_3PHASE_CTRL45 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl45;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl45 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL45;

typedef struct{
    unsigned  CSI_3PHASE_CTRL46 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl46;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl46 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL46;

typedef struct{
    unsigned  CSI_3PHASE_CTRL47 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl47;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl47 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL47;

typedef struct{
    unsigned  CSI_3PHASE_CTRL48 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl48;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl48 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL48;

typedef struct{
    unsigned  CSI_3PHASE_CTRL49 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl49;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl49 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL49;

typedef struct{
    unsigned  CSI_3PHASE_CTRL50 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl50;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl50 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL50;

typedef struct{
    unsigned  CSI_3PHASE_CTRL51 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl51;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl51 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL51;

typedef struct{
    unsigned  CSI_3PHASE_CTRL52 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl52;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl52 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL52;

typedef struct{
    unsigned  CSI_3PHASE_CTRL53 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl53;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl53 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL53;

typedef struct{
    unsigned  CSI_3PHASE_CTRL54 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl54;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl54 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL54;

typedef struct{
    unsigned  CSI_3PHASE_CTRL55 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl55;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_ctrl55 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_CTRL55;

typedef struct{
    unsigned  CSI_3PHASE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS0;

typedef struct{
    unsigned  CSI_3PHASE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS1;

typedef struct{
    unsigned  CSI_3PHASE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS2;

typedef struct{
    unsigned  CSI_3PHASE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS3;

typedef struct{
    unsigned  CSI_3PHASE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS4;

typedef struct{
    unsigned  CSI_3PHASE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS5;

typedef struct{
    unsigned  CSI_3PHASE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS6;

typedef struct{
    unsigned  CSI_3PHASE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln1_csi_3phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN1_CSI_3PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL0;

typedef struct{
    unsigned  CSI_LANE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL1;

typedef struct{
    unsigned  CSI_LANE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL2;

typedef struct{
    unsigned  CSI_LANE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL3;

typedef struct{
    unsigned  CSI_LANE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL4;

typedef struct{
    unsigned  CSI_LANE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL5;

typedef struct{
    unsigned  CSI_LANE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL6;

typedef struct{
    unsigned  CSI_LANE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL7;

typedef struct{
    unsigned  CSI_LANE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL8;

typedef struct{
    unsigned  CSI_LANE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL9;

typedef struct{
    unsigned  CSI_LANE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL10;

typedef struct{
    unsigned  CSI_LANE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL11;

typedef struct{
    unsigned  CSI_LANE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL12;

typedef struct{
    unsigned  CSI_LANE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL13;

typedef struct{
    unsigned  CSI_LANE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL14;

typedef struct{
    unsigned  CSI_LANE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL15;

typedef struct{
    unsigned  CSI_LANE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL16;

typedef struct{
    unsigned  CSI_LANE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL17;

typedef struct{
    unsigned  CSI_LANE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL18;

typedef struct{
    unsigned  CSI_LANE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL19;

typedef struct{
    unsigned  CSI_LANE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL20;

typedef struct{
    unsigned  CSI_LANE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL21;

typedef struct{
    unsigned  CSI_LANE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL22;

typedef struct{
    unsigned  CSI_LANE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL23;

typedef struct{
    unsigned  CSI_LANE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL24;

typedef struct{
    unsigned  CSI_LANE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL25;

typedef struct{
    unsigned  CSI_LANE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL26;

typedef struct{
    unsigned  CSI_LANE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL27;

typedef struct{
    unsigned  CSI_LANE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL28;

typedef struct{
    unsigned  CSI_LANE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL29;

typedef struct{
    unsigned  CSI_LANE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL30;

typedef struct{
    unsigned  CSI_LANE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL31;

typedef struct{
    unsigned  CSI_LANE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL32;

typedef struct{
    unsigned  CSI_LANE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL33;

typedef struct{
    unsigned  CSI_LANE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL34;

typedef struct{
    unsigned  CSI_LANE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_CTRL35;

typedef struct{
    unsigned  CSI_LANE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS0;

typedef struct{
    unsigned  CSI_LANE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS1;

typedef struct{
    unsigned  CSI_LANE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS2;

typedef struct{
    unsigned  CSI_LANE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS3;

typedef struct{
    unsigned  CSI_LANE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS4;

typedef struct{
    unsigned  CSI_LANE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS5;

typedef struct{
    unsigned  CSI_LANE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS6;

typedef struct{
    unsigned  CSI_LANE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS8;

typedef struct{
    unsigned  CSI_LANE_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS9;

typedef struct{
    unsigned  CSI_LANE_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS10;

typedef struct{
    unsigned  CSI_LANE_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS11;

typedef struct{
    unsigned  CSI_LANE_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS12;

typedef struct{
    unsigned  CSI_LANE_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS13;

typedef struct{
    unsigned  CSI_LANE_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS14;

typedef struct{
    unsigned  CSI_LANE_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln2_csi_2phase_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN2_CSI_2PHASE_STATUS15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL0;

typedef struct{
    unsigned  CSI_3PHASE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL1;

typedef struct{
    unsigned  CSI_3PHASE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL2;

typedef struct{
    unsigned  CSI_3PHASE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL3;

typedef struct{
    unsigned  CSI_3PHASE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL4;

typedef struct{
    unsigned  CSI_3PHASE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL5;

typedef struct{
    unsigned  CSI_3PHASE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL6;

typedef struct{
    unsigned  CSI_3PHASE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL7;

typedef struct{
    unsigned  CSI_3PHASE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL8;

typedef struct{
    unsigned  CSI_3PHASE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL9;

typedef struct{
    unsigned  CSI_3PHASE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL10;

typedef struct{
    unsigned  CSI_3PHASE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL11;

typedef struct{
    unsigned  CSI_3PHASE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL12;

typedef struct{
    unsigned  CSI_3PHASE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL13;

typedef struct{
    unsigned  CSI_3PHASE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL14;

typedef struct{
    unsigned  CSI_3PHASE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL16;

typedef struct{
    unsigned  CSI_3PHASE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL17;

typedef struct{
    unsigned  CSI_3PHASE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL18;

typedef struct{
    unsigned  CSI_3PHASE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL19;

typedef struct{
    unsigned  CSI_3PHASE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL20;

typedef struct{
    unsigned  CSI_3PHASE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL21;

typedef struct{
    unsigned  CSI_3PHASE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL22;

typedef struct{
    unsigned  CSI_3PHASE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL23;

typedef struct{
    unsigned  CSI_3PHASE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL24;

typedef struct{
    unsigned  CSI_3PHASE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL25;

typedef struct{
    unsigned  CSI_3PHASE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL26;

typedef struct{
    unsigned  CSI_3PHASE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL27;

typedef struct{
    unsigned  CSI_3PHASE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL28;

typedef struct{
    unsigned  CSI_3PHASE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL29;

typedef struct{
    unsigned  CSI_3PHASE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL30;

typedef struct{
    unsigned  CSI_3PHASE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL31;

typedef struct{
    unsigned  CSI_3PHASE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL32;

typedef struct{
    unsigned  CSI_3PHASE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL33;

typedef struct{
    unsigned  CSI_3PHASE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL34;

typedef struct{
    unsigned  CSI_3PHASE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL35;

typedef struct{
    unsigned  CSI_3PHASE_CTRL36 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl36;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl36 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL36;

typedef struct{
    unsigned  CSI_3PHASE_CTRL37 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl37;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl37 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL37;

typedef struct{
    unsigned  CSI_3PHASE_CTRL38 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl38;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl38 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL38;

typedef struct{
    unsigned  CSI_3PHASE_CTRL39 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl39;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl39 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL39;

typedef struct{
    unsigned  CSI_3PHASE_CTRL40 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl40;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl40 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL40;

typedef struct{
    unsigned  CSI_3PHASE_CTRL41 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl41;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl41 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL41;

typedef struct{
    unsigned  CSI_3PHASE_CTRL42 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl42;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl42 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL42;

typedef struct{
    unsigned  CSI_3PHASE_CTRL43 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl43;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl43 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL43;

typedef struct{
    unsigned  CSI_3PHASE_CTRL44 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl44;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl44 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL44;

typedef struct{
    unsigned  CSI_3PHASE_CTRL45 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl45;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl45 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL45;

typedef struct{
    unsigned  CSI_3PHASE_CTRL46 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl46;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl46 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL46;

typedef struct{
    unsigned  CSI_3PHASE_CTRL47 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl47;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl47 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL47;

typedef struct{
    unsigned  CSI_3PHASE_CTRL48 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl48;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl48 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL48;

typedef struct{
    unsigned  CSI_3PHASE_CTRL49 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl49;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl49 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL49;

typedef struct{
    unsigned  CSI_3PHASE_CTRL50 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl50;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl50 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL50;

typedef struct{
    unsigned  CSI_3PHASE_CTRL51 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl51;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl51 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL51;

typedef struct{
    unsigned  CSI_3PHASE_CTRL52 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl52;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl52 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL52;

typedef struct{
    unsigned  CSI_3PHASE_CTRL53 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl53;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl53 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL53;

typedef struct{
    unsigned  CSI_3PHASE_CTRL54 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl54;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl54 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL54;

typedef struct{
    unsigned  CSI_3PHASE_CTRL55 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl55;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_ctrl55 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_CTRL55;

typedef struct{
    unsigned  CSI_3PHASE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS0;

typedef struct{
    unsigned  CSI_3PHASE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS1;

typedef struct{
    unsigned  CSI_3PHASE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS2;

typedef struct{
    unsigned  CSI_3PHASE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS3;

typedef struct{
    unsigned  CSI_3PHASE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS4;

typedef struct{
    unsigned  CSI_3PHASE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS5;

typedef struct{
    unsigned  CSI_3PHASE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS6;

typedef struct{
    unsigned  CSI_3PHASE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln3_csi_3phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN3_CSI_3PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL0;

typedef struct{
    unsigned  CSI_LANE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL1;

typedef struct{
    unsigned  CSI_LANE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL2;

typedef struct{
    unsigned  CSI_LANE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL3;

typedef struct{
    unsigned  CSI_LANE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL4;

typedef struct{
    unsigned  CSI_LANE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL5;

typedef struct{
    unsigned  CSI_LANE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL6;

typedef struct{
    unsigned  CSI_LANE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL7;

typedef struct{
    unsigned  CSI_LANE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL8;

typedef struct{
    unsigned  CSI_LANE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL9;

typedef struct{
    unsigned  CSI_LANE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL10;

typedef struct{
    unsigned  CSI_LANE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL11;

typedef struct{
    unsigned  CSI_LANE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL12;

typedef struct{
    unsigned  CSI_LANE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL13;

typedef struct{
    unsigned  CSI_LANE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL14;

typedef struct{
    unsigned  CSI_LANE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL15;

typedef struct{
    unsigned  CSI_LANE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL16;

typedef struct{
    unsigned  CSI_LANE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL17;

typedef struct{
    unsigned  CSI_LANE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL18;

typedef struct{
    unsigned  CSI_LANE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL19;

typedef struct{
    unsigned  CSI_LANE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL20;

typedef struct{
    unsigned  CSI_LANE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL21;

typedef struct{
    unsigned  CSI_LANE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL22;

typedef struct{
    unsigned  CSI_LANE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL23;

typedef struct{
    unsigned  CSI_LANE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL24;

typedef struct{
    unsigned  CSI_LANE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL25;

typedef struct{
    unsigned  CSI_LANE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL26;

typedef struct{
    unsigned  CSI_LANE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL27;

typedef struct{
    unsigned  CSI_LANE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL28;

typedef struct{
    unsigned  CSI_LANE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL29;

typedef struct{
    unsigned  CSI_LANE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL30;

typedef struct{
    unsigned  CSI_LANE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL31;

typedef struct{
    unsigned  CSI_LANE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL32;

typedef struct{
    unsigned  CSI_LANE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL33;

typedef struct{
    unsigned  CSI_LANE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL34;

typedef struct{
    unsigned  CSI_LANE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_CTRL35;

typedef struct{
    unsigned  CSI_LANE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS0;

typedef struct{
    unsigned  CSI_LANE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS1;

typedef struct{
    unsigned  CSI_LANE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS2;

typedef struct{
    unsigned  CSI_LANE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS3;

typedef struct{
    unsigned  CSI_LANE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS4;

typedef struct{
    unsigned  CSI_LANE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS5;

typedef struct{
    unsigned  CSI_LANE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS6;

typedef struct{
    unsigned  CSI_LANE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS8;

typedef struct{
    unsigned  CSI_LANE_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS9;

typedef struct{
    unsigned  CSI_LANE_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS10;

typedef struct{
    unsigned  CSI_LANE_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS11;

typedef struct{
    unsigned  CSI_LANE_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS12;

typedef struct{
    unsigned  CSI_LANE_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS13;

typedef struct{
    unsigned  CSI_LANE_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS14;

typedef struct{
    unsigned  CSI_LANE_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln4_csi_2phase_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN4_CSI_2PHASE_STATUS15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL0;

typedef struct{
    unsigned  CSI_3PHASE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL1;

typedef struct{
    unsigned  CSI_3PHASE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL2;

typedef struct{
    unsigned  CSI_3PHASE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL3;

typedef struct{
    unsigned  CSI_3PHASE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL4;

typedef struct{
    unsigned  CSI_3PHASE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL5;

typedef struct{
    unsigned  CSI_3PHASE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL6;

typedef struct{
    unsigned  CSI_3PHASE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL7;

typedef struct{
    unsigned  CSI_3PHASE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL8;

typedef struct{
    unsigned  CSI_3PHASE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL9;

typedef struct{
    unsigned  CSI_3PHASE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL10;

typedef struct{
    unsigned  CSI_3PHASE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL11;

typedef struct{
    unsigned  CSI_3PHASE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL12;

typedef struct{
    unsigned  CSI_3PHASE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL13;

typedef struct{
    unsigned  CSI_3PHASE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL14;

typedef struct{
    unsigned  CSI_3PHASE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL15;

typedef struct{
    unsigned  CSI_3PHASE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL16;

typedef struct{
    unsigned  CSI_3PHASE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL17;

typedef struct{
    unsigned  CSI_3PHASE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL18;

typedef struct{
    unsigned  CSI_3PHASE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL19;

typedef struct{
    unsigned  CSI_3PHASE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL20;

typedef struct{
    unsigned  CSI_3PHASE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL21;

typedef struct{
    unsigned  CSI_3PHASE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL22;

typedef struct{
    unsigned  CSI_3PHASE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL23;

typedef struct{
    unsigned  CSI_3PHASE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL24;

typedef struct{
    unsigned  CSI_3PHASE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL25;

typedef struct{
    unsigned  CSI_3PHASE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL26;

typedef struct{
    unsigned  CSI_3PHASE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL27;

typedef struct{
    unsigned  CSI_3PHASE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL28;

typedef struct{
    unsigned  CSI_3PHASE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL29;

typedef struct{
    unsigned  CSI_3PHASE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL30;

typedef struct{
    unsigned  CSI_3PHASE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL31;

typedef struct{
    unsigned  CSI_3PHASE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL32;

typedef struct{
    unsigned  CSI_3PHASE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL33;

typedef struct{
    unsigned  CSI_3PHASE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL34;

typedef struct{
    unsigned  CSI_3PHASE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL35;

typedef struct{
    unsigned  CSI_3PHASE_CTRL36 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl36;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl36 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL36;

typedef struct{
    unsigned  CSI_3PHASE_CTRL37 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl37;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl37 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL37;

typedef struct{
    unsigned  CSI_3PHASE_CTRL38 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl38;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl38 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL38;

typedef struct{
    unsigned  CSI_3PHASE_CTRL39 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl39;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl39 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL39;

typedef struct{
    unsigned  CSI_3PHASE_CTRL40 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl40;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl40 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL40;

typedef struct{
    unsigned  CSI_3PHASE_CTRL41 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl41;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl41 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL41;

typedef struct{
    unsigned  CSI_3PHASE_CTRL42 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl42;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl42 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL42;

typedef struct{
    unsigned  CSI_3PHASE_CTRL43 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl43;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl43 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL43;

typedef struct{
    unsigned  CSI_3PHASE_CTRL44 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl44;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl44 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL44;

typedef struct{
    unsigned  CSI_3PHASE_CTRL45 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl45;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl45 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL45;

typedef struct{
    unsigned  CSI_3PHASE_CTRL46 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl46;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl46 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL46;

typedef struct{
    unsigned  CSI_3PHASE_CTRL47 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl47;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl47 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL47;

typedef struct{
    unsigned  CSI_3PHASE_CTRL48 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl48;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl48 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL48;

typedef struct{
    unsigned  CSI_3PHASE_CTRL49 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl49;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl49 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL49;

typedef struct{
    unsigned  CSI_3PHASE_CTRL50 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl50;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl50 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL50;

typedef struct{
    unsigned  CSI_3PHASE_CTRL51 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl51;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl51 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL51;

typedef struct{
    unsigned  CSI_3PHASE_CTRL52 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl52;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl52 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL52;

typedef struct{
    unsigned  CSI_3PHASE_CTRL53 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl53;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl53 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL53;

typedef struct{
    unsigned  CSI_3PHASE_CTRL54 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl54;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl54 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL54;

typedef struct{
    unsigned  CSI_3PHASE_CTRL55 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl55;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_ctrl55 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_CTRL55;

typedef struct{
    unsigned  CSI_3PHASE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS0;

typedef struct{
    unsigned  CSI_3PHASE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS1;

typedef struct{
    unsigned  CSI_3PHASE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS2;

typedef struct{
    unsigned  CSI_3PHASE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS3;

typedef struct{
    unsigned  CSI_3PHASE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS4;

typedef struct{
    unsigned  CSI_3PHASE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS5;

typedef struct{
    unsigned  CSI_3PHASE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS6;

typedef struct{
    unsigned  CSI_3PHASE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln5_csi_3phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN5_CSI_3PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL0;

typedef struct{
    unsigned  CSI_LANE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL1;

typedef struct{
    unsigned  CSI_LANE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL2;

typedef struct{
    unsigned  CSI_LANE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL3;

typedef struct{
    unsigned  CSI_LANE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL4;

typedef struct{
    unsigned  CSI_LANE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL5;

typedef struct{
    unsigned  CSI_LANE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL6;

typedef struct{
    unsigned  CSI_LANE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL7;

typedef struct{
    unsigned  CSI_LANE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL8;

typedef struct{
    unsigned  CSI_LANE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL9;

typedef struct{
    unsigned  CSI_LANE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL10;

typedef struct{
    unsigned  CSI_LANE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL11;

typedef struct{
    unsigned  CSI_LANE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL12;

typedef struct{
    unsigned  CSI_LANE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL13;

typedef struct{
    unsigned  CSI_LANE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL14;

typedef struct{
    unsigned  CSI_LANE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL15;

typedef struct{
    unsigned  CSI_LANE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL16;

typedef struct{
    unsigned  CSI_LANE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL17;

typedef struct{
    unsigned  CSI_LANE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL18;

typedef struct{
    unsigned  CSI_LANE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL19;

typedef struct{
    unsigned  CSI_LANE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL20;

typedef struct{
    unsigned  CSI_LANE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL21;

typedef struct{
    unsigned  CSI_LANE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL22;

typedef struct{
    unsigned  CSI_LANE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL23;

typedef struct{
    unsigned  CSI_LANE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL24;

typedef struct{
    unsigned  CSI_LANE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL25;

typedef struct{
    unsigned  CSI_LANE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL26;

typedef struct{
    unsigned  CSI_LANE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL27;

typedef struct{
    unsigned  CSI_LANE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL28;

typedef struct{
    unsigned  CSI_LANE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL29;

typedef struct{
    unsigned  CSI_LANE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL30;

typedef struct{
    unsigned  CSI_LANE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL31;

typedef struct{
    unsigned  CSI_LANE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL32;

typedef struct{
    unsigned  CSI_LANE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL33;

typedef struct{
    unsigned  CSI_LANE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL34;

typedef struct{
    unsigned  CSI_LANE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_CTRL35;

typedef struct{
    unsigned  CSI_LANE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS0;

typedef struct{
    unsigned  CSI_LANE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS1;

typedef struct{
    unsigned  CSI_LANE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS2;

typedef struct{
    unsigned  CSI_LANE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS3;

typedef struct{
    unsigned  CSI_LANE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS4;

typedef struct{
    unsigned  CSI_LANE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS5;

typedef struct{
    unsigned  CSI_LANE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS6;

typedef struct{
    unsigned  CSI_LANE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS8;

typedef struct{
    unsigned  CSI_LANE_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS9;

typedef struct{
    unsigned  CSI_LANE_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS10;

typedef struct{
    unsigned  CSI_LANE_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS11;

typedef struct{
    unsigned  CSI_LANE_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS12;

typedef struct{
    unsigned  CSI_LANE_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS13;

typedef struct{
    unsigned  CSI_LANE_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS14;

typedef struct{
    unsigned  CSI_LANE_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ln6_csi_2phase_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LN6_CSI_2PHASE_STATUS15;

typedef struct{
    unsigned  CSI_LANE_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL0;

typedef struct{
    unsigned  CSI_LANE_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL1;

typedef struct{
    unsigned  CSI_LANE_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL2;

typedef struct{
    unsigned  CSI_LANE_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL3;

typedef struct{
    unsigned  CSI_LANE_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL4;

typedef struct{
    unsigned  CSI_LANE_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL5;

typedef struct{
    unsigned  CSI_LANE_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL6;

typedef struct{
    unsigned  CSI_LANE_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL7;

typedef struct{
    unsigned  CSI_LANE_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL8;

typedef struct{
    unsigned  CSI_LANE_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL9;

typedef struct{
    unsigned  CSI_LANE_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL10;

typedef struct{
    unsigned  CSI_LANE_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL11;

typedef struct{
    unsigned  CSI_LANE_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL12;

typedef struct{
    unsigned  CSI_LANE_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL13;

typedef struct{
    unsigned  CSI_LANE_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL14;

typedef struct{
    unsigned  CSI_LANE_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL15;

typedef struct{
    unsigned  CSI_LANE_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL16;

typedef struct{
    unsigned  CSI_LANE_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL17;

typedef struct{
    unsigned  CSI_LANE_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL18;

typedef struct{
    unsigned  CSI_LANE_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL19;

typedef struct{
    unsigned  CSI_LANE_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL20;

typedef struct{
    unsigned  CSI_LANE_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL21;

typedef struct{
    unsigned  CSI_LANE_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL22;

typedef struct{
    unsigned  CSI_LANE_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL23;

typedef struct{
    unsigned  CSI_LANE_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL24;

typedef struct{
    unsigned  CSI_LANE_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL25;

typedef struct{
    unsigned  CSI_LANE_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL26;

typedef struct{
    unsigned  CSI_LANE_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL27;

typedef struct{
    unsigned  CSI_LANE_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL28;

typedef struct{
    unsigned  CSI_LANE_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL29;

typedef struct{
    unsigned  CSI_LANE_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL30;

typedef struct{
    unsigned  CSI_LANE_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL31;

typedef struct{
    unsigned  CSI_LANE_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL32;

typedef struct{
    unsigned  CSI_LANE_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL33;

typedef struct{
    unsigned  CSI_LANE_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL34;

typedef struct{
    unsigned  CSI_LANE_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_CTRL35;

typedef struct{
    unsigned  CSI_LANE_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS0;

typedef struct{
    unsigned  CSI_LANE_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS1;

typedef struct{
    unsigned  CSI_LANE_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS2;

typedef struct{
    unsigned  CSI_LANE_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS3;

typedef struct{
    unsigned  CSI_LANE_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS4;

typedef struct{
    unsigned  CSI_LANE_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS5;

typedef struct{
    unsigned  CSI_LANE_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS6;

typedef struct{
    unsigned  CSI_LANE_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS7;

typedef struct{
    unsigned  CSI_LANE_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS8;

typedef struct{
    unsigned  CSI_LANE_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS9;

typedef struct{
    unsigned  CSI_LANE_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS10;

typedef struct{
    unsigned  CSI_LANE_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS11;

typedef struct{
    unsigned  CSI_LANE_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS12;

typedef struct{
    unsigned  CSI_LANE_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS13;

typedef struct{
    unsigned  CSI_LANE_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS14;

typedef struct{
    unsigned  CSI_LANE_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_lnck_csi_2phase_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_LNCK_CSI_2PHASE_STATUS15;

typedef struct{
    unsigned  CSI_COMMON_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL0;

typedef struct{
    unsigned  CSI_COMMON_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL1;

typedef struct{
    unsigned  CSI_COMMON_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL2;

typedef struct{
    unsigned  CSI_COMMON_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL3;

typedef struct{
    unsigned  CSI_COMMON_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL4;

typedef struct{
    unsigned  CSI_COMMON_CTRL5_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_CTRL5_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_CTRL5_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_CTRL5_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_CTRL5_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_CTRL5_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_CTRL5_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_CTRL5_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL5;

typedef struct{
    unsigned  CSI_COMMON_CTRL6_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_CTRL6_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_CTRL6_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_CTRL6_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_CTRL6_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_CTRL6_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_CTRL6_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_CTRL6_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL6;

typedef struct{
    unsigned  CSI_COMMON_CTRL7_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_CTRL7_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_CTRL7_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_CTRL7_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_CTRL7_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_CTRL7_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_CTRL7_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_CTRL7_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL7;

typedef struct{
    unsigned  CSI_COMMON_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL8;

typedef struct{
    unsigned  CSI_COMMON_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL9;

typedef struct{
    unsigned  CSI_COMMON_CTRL10_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_CTRL10_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_CTRL10_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_CTRL10_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_CTRL10_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_CTRL10_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_CTRL10_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_CTRL10_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL10;

typedef struct{
    unsigned  CSI_COMMON_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL11;

typedef struct{
    unsigned  CSI_COMMON_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL12;

typedef struct{
    unsigned  CSI_COMMON_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL13;

typedef struct{
    unsigned  CSI_COMMON_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL14;

typedef struct{
    unsigned  CSI_COMMON_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL15;

typedef struct{
    unsigned  CSI_COMMON_CTRL16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL16;

typedef struct{
    unsigned  CSI_COMMON_CTRL17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL17;

typedef struct{
    unsigned  CSI_COMMON_CTRL18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL18;

typedef struct{
    unsigned  CSI_COMMON_CTRL19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL19;

typedef struct{
    unsigned  CSI_COMMON_CTRL20 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl20;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl20 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL20;

typedef struct{
    unsigned  CSI_COMMON_CTRL21 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl21;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl21 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL21;

typedef struct{
    unsigned  CSI_COMMON_CTRL22 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl22;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl22 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL22;

typedef struct{
    unsigned  CSI_COMMON_CTRL23 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl23;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl23 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL23;

typedef struct{
    unsigned  CSI_COMMON_CTRL24 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl24;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl24 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL24;

typedef struct{
    unsigned  CSI_COMMON_CTRL25 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl25;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl25 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL25;

typedef struct{
    unsigned  CSI_COMMON_CTRL26 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl26;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl26 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL26;

typedef struct{
    unsigned  CSI_COMMON_CTRL27 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl27;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl27 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL27;

typedef struct{
    unsigned  CSI_COMMON_CTRL28 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl28;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl28 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL28;

typedef struct{
    unsigned  CSI_COMMON_CTRL29 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl29;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl29 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL29;

typedef struct{
    unsigned  CSI_COMMON_CTRL30 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl30;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl30 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL30;

typedef struct{
    unsigned  CSI_COMMON_CTRL31 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl31;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl31 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL31;

typedef struct{
    unsigned  CSI_COMMON_CTRL32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl32;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl32 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL32;

typedef struct{
    unsigned  CSI_COMMON_CTRL33 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl33;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl33 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL33;

typedef struct{
    unsigned  CSI_COMMON_CTRL34 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl34;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl34 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL34;

typedef struct{
    unsigned  CSI_COMMON_CTRL35 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl35;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl35 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL35;

typedef struct{
    unsigned  CSI_COMMON_CTRL36 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl36;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl36 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL36;

typedef struct{
    unsigned  CSI_COMMON_CTRL37 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl37;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl37 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL37;

typedef struct{
    unsigned  CSI_COMMON_CTRL38 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl38;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl38 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL38;

typedef struct{
    unsigned  CSI_COMMON_CTRL39 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl39;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl39 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL39;

typedef struct{
    unsigned  CSI_COMMON_CTRL40 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl40;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl40 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL40;

typedef struct{
    unsigned  CSI_COMMON_CTRL41 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl41;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl41 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL41;

typedef struct{
    unsigned  CSI_COMMON_CTRL42 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl42;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl42 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL42;

typedef struct{
    unsigned  CSI_COMMON_CTRL43 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl43;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_ctrl43 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_CTRL43;

typedef struct{
    unsigned  CSI_COMMON_STATUS0_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS0_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS0_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS0_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS0_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS0_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS0_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS0_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS0;

typedef struct{
    unsigned  CSI_COMMON_STATUS1_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS1_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS1_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS1_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS1_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS1_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS1_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS1_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS1;

typedef struct{
    unsigned  CSI_COMMON_STATUS2_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS2_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS2_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS2_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS2_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS2_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS2_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS2_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS2;

typedef struct{
    unsigned  CSI_COMMON_STATUS3_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS3_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS3_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS3_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS3_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS3_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS3_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS3_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS3;

typedef struct{
    unsigned  CSI_COMMON_STATUS4_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS4_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS4_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS4_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS4_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS4_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS4_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS4_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS4;

typedef struct{
    unsigned  CSI_COMMON_STATUS5_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS5_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS5_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS5_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS5_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS5_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS5_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS5_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS5;

typedef struct{
    unsigned  CSI_COMMON_STATUS6_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS6_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS6_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS6_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS6_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS6_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS6_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS6_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS6;

typedef struct{
    unsigned  CSI_COMMON_STATUS7_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS7_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS7_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS7_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS7_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS7_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS7_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS7_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS7;

typedef struct{
    unsigned  CSI_COMMON_STATUS8_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS8_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS8_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS8_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS8_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS8_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS8_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS8_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS8;

typedef struct{
    unsigned  CSI_COMMON_STATUS9_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS9_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS9_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS9_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS9_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS9_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS9_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS9_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS9;

typedef struct{
    unsigned  CSI_COMMON_STATUS10_0 : 1; /* 0:0 */
    unsigned  CSI_COMMON_STATUS10_1 : 1; /* 1:1 */
    unsigned  CSI_COMMON_STATUS10_2 : 1; /* 2:2 */
    unsigned  CSI_COMMON_STATUS10_3 : 1; /* 3:3 */
    unsigned  CSI_COMMON_STATUS10_4 : 1; /* 4:4 */
    unsigned  CSI_COMMON_STATUS10_5 : 1; /* 5:5 */
    unsigned  CSI_COMMON_STATUS10_6 : 1; /* 6:6 */
    unsigned  CSI_COMMON_STATUS10_7 : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS10;

typedef struct{
    unsigned  CSI_COMMON_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS11;

typedef struct{
    unsigned  CSI_COMMON_STATUS12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS12;

typedef struct{
    unsigned  CSI_COMMON_STATUS13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS13;

typedef struct{
    unsigned  CSI_COMMON_STATUS14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS14;

typedef struct{
    unsigned  CSI_COMMON_STATUS15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS15;

typedef struct{
    unsigned  CSI_COMMON_STATUS16 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status16;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status16 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS16;

typedef struct{
    unsigned  CSI_COMMON_STATUS17 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status17;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status17 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS17;

typedef struct{
    unsigned  CSI_COMMON_STATUS18 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status18;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status18 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS18;

typedef struct{
    unsigned  CSI_COMMON_STATUS19 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status19;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_cmn_csi_common_status19 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_CMN_CSI_COMMON_STATUS19;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext0_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT0_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext1_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT1_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext2_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT2_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext3_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT3_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext4_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT4_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext5_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT5_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_ext6_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXT6_CSI_EXTRA_STATUS11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL0;

typedef struct{
    unsigned  CSI_EXTRA_CTRL1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL1;

typedef struct{
    unsigned  CSI_EXTRA_CTRL2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL2;

typedef struct{
    unsigned  CSI_EXTRA_CTRL3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL3;

typedef struct{
    unsigned  CSI_EXTRA_CTRL4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL4;

typedef struct{
    unsigned  CSI_EXTRA_CTRL5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL5;

typedef struct{
    unsigned  CSI_EXTRA_CTRL6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL6;

typedef struct{
    unsigned  CSI_EXTRA_CTRL7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL7;

typedef struct{
    unsigned  CSI_EXTRA_CTRL8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL8;

typedef struct{
    unsigned  CSI_EXTRA_CTRL9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL9;

typedef struct{
    unsigned  CSI_EXTRA_CTRL10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL10;

typedef struct{
    unsigned  CSI_EXTRA_CTRL11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL11;

typedef struct{
    unsigned  CSI_EXTRA_CTRL12 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl12;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl12 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL12;

typedef struct{
    unsigned  CSI_EXTRA_CTRL13 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl13;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl13 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL13;

typedef struct{
    unsigned  CSI_EXTRA_CTRL14 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl14;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl14 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL14;

typedef struct{
    unsigned  CSI_EXTRA_CTRL15 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl15;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_ctrl15 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_CTRL15;

typedef struct{
    unsigned  CSI_EXTRA_STATUS0 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status0;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status0 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS0;

typedef struct{
    unsigned  CSI_EXTRA_STATUS1 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status1;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status1 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS1;

typedef struct{
    unsigned  CSI_EXTRA_STATUS2 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status2;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status2 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS2;

typedef struct{
    unsigned  CSI_EXTRA_STATUS3 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status3;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status3 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS3;

typedef struct{
    unsigned  CSI_EXTRA_STATUS4 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status4;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status4 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS4;

typedef struct{
    unsigned  CSI_EXTRA_STATUS5 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status5;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status5 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS5;

typedef struct{
    unsigned  CSI_EXTRA_STATUS6 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status6;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status6 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS6;

typedef struct{
    unsigned  CSI_EXTRA_STATUS7 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status7;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status7 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS7;

typedef struct{
    unsigned  CSI_EXTRA_STATUS8 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status8;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status8 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS8;

typedef struct{
    unsigned  CSI_EXTRA_STATUS9 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status9;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status9 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS9;

typedef struct{
    unsigned  CSI_EXTRA_STATUS10 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status10;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status10 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS10;

typedef struct{
    unsigned  CSI_EXTRA_STATUS11 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status11;

typedef union{
    _cm_mipi_csi_3phase_phy_0_csiphy_extck_csi_extra_status11 bitfields,bits;
    unsigned int u32All;

} CM_MIPI_CSI_3PHASE_PHY_0_CSIPHY_EXTCK_CSI_EXTRA_STATUS11;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/
#endif // TITAN170_CM_MIPI_CSI_3PHASE_H
